Electronic Era (1920–1960)Semiconductor Physics & Microelectronics

Noyce Monolithic Planar Integrated Circuit

US 2,981,877

Vapor-Deposited Aluminum Interconnects Over Thermally Grown Silicon Dioxide Passivation

Inventor(s)Robert N. Noyce

Grant Date1961-04-25

Filing Date1959-07-30

LocationLos Altos, California

Noyce's 1959 Fairchild filing: print aluminum interconnects on top of thermally grown SiO₂ so they can cross p–n junctions on a single silicon die. Kilby had already shown that components could share a semiconductor body; this patent is how you wire them without gold flying leads.

USPTO PDF

Engineering Analysis & Physical Principles

How It Works: Step-by-Step Mechanical & Physical Breakdown

In 1958, computers were limited by the 'Tyranny of Numbers': circuits required millions of discrete transistors, diodes, and resistors hand-soldered together with tiny wires. If a single solder joint failed, the entire room-sized computer crashed. Jack Kilby at Texas Instruments created the first integrated circuit in 1958 by connecting components on a germanium bar with hand-glued gold flying wires. Robert Noyce at Fairchild Semiconductor made the definitive breakthrough that launched the computer age: he realized that by using the planar process with a glass insulating layer of silicon dioxide ($SiO_2$), aluminum wiring could be evaporated directly across the chip's surface, printing millions of transistors and their interconnections simultaneously in one solid crystal.

The Core Breakthrough Mechanism

A single crystal silicon wafer undergoes thermal oxidation to form a tough, insulating layer of silicon dioxide glass ( $SiO_2$ ). Photolithography etches microscopic contact holes through the glass into active p-n junctions below. Aluminum metal is vapor-deposited across the entire surface and etched into flat microscopic wires that travel over the glass insulator, directly connecting transistors without a single loose wire.

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Detailed Component Architecture

1Thermally Grown Silicon Dioxide (SiO2) Passivation

A micro-thin layer of pure glass grown on the silicon surface by heating with oxygen.

Has high dielectric breakdown strength ( $E_{bd} \approx 10^7\text{ V/cm}$ ), insulating aluminum wires from shorting against the underlying silicon p-n junctions.

19th-C. Term: Oxide coating adherent to the semiconductor surfaceModern: Interlayer dielectric (ILD) / Thermal oxide passivation

2Vapor-Deposited Aluminum Metallization Leads

Thin flat aluminum stripes vacuum-evaporated over the oxide.

Forms low-resistance ohmic contacts ( $R_c < 10^{-6}\,\Omega\cdot\text{cm}^2$ ) at exposed silicon contact windows while routing signals across the glass surface.

19th-C. Term: Conductor adhering to the oxide coating and extending over a junctionModern: Integrated circuit metallization interconnect layer

3Photolithographic Planar Etching

Using photoresist light masks and acid baths to define microscopic circuit geometries.

Enables batch-fabrication of thousands of identical microchips on a single silicon wafer simultaneously.

19th-C. Term: Photo-engraving and selective chemical etchingModern: Semiconductor photolithography & plasma etching

Governing Physical Equations & Principles

Planar Solid-State Monolithic Integration

N_{components} \propto e^{\alpha t}, \quad A_{die} = \sum A_{transistors} + A_{interconnect}

Noyce's planar metallization solved the interconnect bottleneck, enabling Moore's Law scaling from single transistors to billions of logic gates on a microchip.

Dielectric Isolation & Ohmic Contact Formation

J_{tunnel} = J_0 \exp\left(-\frac{4\pi \sqrt{2m^* \Phi_B}}{h} d\right), \quad C_{ox} = \frac{\varepsilon_{ox} A}{t_{ox}}

Thermal SiO₂ provides near-infinite DC isolation resistance (>10¹⁴ Ω·cm) while permitting dense multi-layer metal interconnects.

Why It Still Matters

A modern SoC is still Noyce's stack: oxide on silicon, contact windows, metal that is allowed to run over junctions. Damascene copper and low-κ dielectrics changed the materials, not the topology. Intel, which Noyce co-founded in 1968, still ships that topology by the billion.

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Claim #1Independent Master Claim

Verbatim Historical Legal Text

“A semiconductor device comprising a body of semiconductor material having a surface, a PN junction extending to said surface, an insulating layer on said surface covering said junction, and an electrical conductor adhering to said insulating layer and extending over said junction, said conductor making electrical contact with said body through an aperture in said insulating layer, substantially as described.”

Plain English Engineering Translation

The master patent claim of the microchip industry: an integrated circuit where a metal conductor adheres to an insulating layer and travels directly over a PN junction to connect semiconductor components.

Key Protected Innovations:

Vapor-deposited metal interconnectsInsulating layer covering PN junctionsMonolithic planar circuit integration

The Historical Bottleneck

By 1958 a large computer was a reliability problem disguised as an electronics problem. A design with 10⁵ transistors implied on the order of 3×10⁵ soldered joints. Each joint was a failure site. The 'tyranny of numbers' (Jack Morton at Bell Labs popularized the phrase) said you could not wire your way to a million devices.

Why Prior Art Failed

•Kilby's 1958 TI germanium bar still used gold flying wires for some connections.
•Mesa transistors left junction edges exposed; contamination killed yield.
•Hybrid modules (Minuteman, IBM SMS) only hid the wiring, they did not remove it.
•Photolithography existed for transistors, not yet for chip-scale metal.

The Breakthrough Insight

“Jean Hoerni's planar process (Fairchild, 1959) left a sheet of SiO₂ over the wafer. Noyce's January 1959 note asked the obvious next question: evaporate aluminum on that glass, etch it into traces, and open windows only where you want contacts. The oxide is both passivation and the printed-circuit board.”

Patent Wars & Legal Litigations

Vs. Jack Kilby and Texas InstrumentsInfringement Challenge

Rival Claim & Defense:

TI said Kilby's US 3,138,743 already covered a plurality of components in one semiconductor body. Fairchild said that claim did not teach planar surface metal running over oxide.

Litigation Conflict:

Interference and infringement dragged through the 1960s. In 1969 the Court of Customs and Patent Appeals credited Noyce with the planar interconnect. Kilby kept the body-of-semiconductor idea. Neither company could ship legally without the other.

Final Resolution & Judicial Outcome:

TI and Fairchild cross-licensed. The industry treated both men as inventors of the IC. Kilby received the 2000 Nobel Prize in Physics; Noyce had died in 1990 and the Nobel is not given posthumously.

After the Grant

US 2,981,877 issued 25 April 1961. Planar TTL and then MOS memories made the flying-lead IC a museum piece within a decade. Noyce spent the 1980s at SEMATECH arguing that the same interconnect physics now needed a national process consortium.

Civilizational Impact

Fairchild's 1961 micrologic parts, then Intel (Noyce, Moore, Grove, 1968), made the planar IC a product line instead of a lab trick. Moore's 1965 density essay is a yield and interconnect essay; it assumes this patent's wiring method.

Historical Fact

Colleagues called Noyce the Mayor of Silicon Valley. The title stuck because he left Fairchild to start Intel and because he ran meetings without the East Coast suit hierarchy the Shockley refugees had walked out on in 1957.

Further Context

The 'traitorous eight' left Shockley Semiconductor in 1957 and founded Fairchild. Hoerni, Noyce, Moore, and Last were in that group. The planar IC is a Fairchild invention in the narrow sense and a Shockley-lab diaspora invention in the wide one.
Early Fairchild metal was aluminum on SiO₂. Purple plague (Au–Al intermetallics) at the package bonds was a 1960s reliability crisis that this patent does not mention and that packaging groups spent a decade fixing.
Gordon Moore's 1965 Electronics article counts components per dollar and per chip. The curve only exists if the wires are printed with the transistors.